A Low-Power Pipelined Implementation of 2D Discrete Wavelet Transform

Discrete wavelet transform has been incorporated as part of the JPEG2000 image compression standard and is being deployed in various portable consumer products. This raises the interest in lowpower design of DWT processor. This paper presents a low-power implementation of a 2-D biorthogonal DWT processor that uses residue number arithmetic. By incorporating a 4-stage pipeline, the processor is able to sustain the same throughput with a lower supply voltage. Hardware complexity reduction and utilization improvement are achieved by resource sharing. Our implementation results show that the design is able to fit into a 1,000,000-gate FPGA device.